Clock signals having multiple phases are used for a write control of DVD or the like or high-speed communication (DDR, QDR, ODR, etc.). In general, the clock signals having multiple phases are generated using, for example, a phase locked loop (PLL) including a phase detector (PD), a charge pump (CP), a low-pass filter (LPF), and an oscillation circuit (a voltage controlled oscillator (VCO), a current controlled oscillator (CCO)). For example, clock signals P0 to P7 having eight phases as shown in FIG. 20A or clock signals P0 to P8 having nine phases as shown in FIG. 20B are generated. Also, the voltage level of a clock signal generated by the oscillation circuit is typically lower than the voltage level of a power supply, and therefore, a level shifter for converting the voltage level of the clock signal into the voltage level of the power supply is required.
FIG. 21A shows a configuration of a general level shifter. In the general level shifter LS90, the gate of an NMOS transistor Mn8 receives a clock signal P(+), and the gate of an NMOS transistor Mn9 receives a clock signal P(−). The phase difference between the clock signal P(+) and the clock signal P(−) is 180°. Also, the gate of a PMOS transistor Mp8 receives a voltage (output signal Q(−)) at a connection point of the transistors Mn9 and a transistor Mp9, and the gate of the PMOS transistor Mp9 receives a voltage (output signal Q(+)) at a connection point of the transistors Mn8 and Mp8. The output signal Q(+) corresponds to the clock signal P(+), and the output signal Q(−) corresponds to the clock signal P(−).
FIG. 21B is a waveform diagram for describing an operation of the level shifter LS90 of FIG. 21A. In the level shifter LS90, when the clock signal P(+) rises, the voltage value of the output signal Q(+) starts decreasing, and when the output signal Q(+) becomes lower than or equal to a threshold voltage ΔVt, the voltage value of the output signal Q(−) starts increasing. Also, when the clock signal P(−) rises, the voltage value of the output signal Q(−) starts decreasing, and when the output signal Q(−) becomes lower than or equal to the threshold voltage ΔVt, the voltage value of the output signal Q(+) starts increasing.
Here, attention is paid to the NMOS transistor Mn8 and the PMOS transistor Mp8. A drive period Ton(n) of the NMOS transistor Mn8 is a period from a rising edge to a falling edge of the clock signal P(+), and a drive period of the PMOS transistor Mp8 is a period from a falling edge to a rising edge of the output signal Q(−).
(Voltage Conversion of Clock Signals Having Even Number of Phases)
When voltage conversion is performed with respect to the clock signals P0 to P7 having eight phases (even number of phases), since there are four pairs of clock signals having a phase difference of 180°, four level shifters LS90a are required as shown in FIG. 22. Specifically, the four level shifters LS90a each receive any one of the clock signals P0 to P3 as the clock signal P(+), and one of the clock signals P4 to P7 that has a phase difference of 180° with respect to the clock signal P(+), as the clock signal P(−). Thereby, output signals Q0 to Q7 corresponding to the clock signals P0 to P7 are output.
(Voltage Conversion of Clock Signals Having Odd Number of Phases)
On the other hand, when voltage conversion is performed with respect to the clock signals P0 to P8 having nine phases (odd number of phases), since there are no clock signals having a phase difference of 180°, inverted clock signals (−P0) to (−P8) as shown in FIG. 23B having nine phases which have a phase difference of 180° with respect to the respective clock signals having nine phases need to be generated using a phase conversion circuit as shown in FIG. 23A. In this case, as shown in FIG. 24, nine level shifters LS90b are required. Specifically, the nine level shifters LS90b each receive any one of the clock signals P0 to P8 as the clock signal P(+), and an inverted clock signal having a phase difference of 180° with respect to the clock signal P(+), as the clock signal P(−). Thereby, output signals Q0 to Q8 corresponding to the clock signals P0 to P8 are output.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2000-307397